#ifndef _FH8856_H_
#define _FH8856_H_


#define RAM_BASE			(0x10000000)
#define DDR_BASE			(0xA0000000)

#define PMU_REG_BASE			(0xF0000000)
#define TIMER_REG_BASE			(0xF0C00000)
#define GPIO0_REG_BASE			(0xF0300000)
#define GPIO1_REG_BASE			(0xF4000000)
#define UART0_REG_BASE			(0xF0700000)
#define UART1_REG_BASE			(0xF0800000)
#define SPI0_REG_BASE			(0xF0500000)
#define SPI1_REG_BASE			(0xF0600000)
#define SPI2_REG_BASE			(0xF0640000)
#define INTC_REG_BASE			(0xE0200000)
#define GMAC_REG_BASE			(0xE0600000)
#define USBC_REG_BASE			(0xE0700000)
#define DMAC_REG_BASE			(0xE0300000)
#define I2C1_REG_BASE			(0xF0B00000)
#define I2C0_REG_BASE			(0xF0200000)
#define SDC0_REG_BASE			(0xE2000000)
#define SDC1_REG_BASE			(0xE2200000)
#define WDT_REG_BASE			(0xF0D00000)
#define PWM_REG_BASE			(0xF0400000)
#define I2S_REG_BASE			(0xF0900000)
#define ACW_REG_BASE			(0xF0A00000)
#define SADC_REG_BASE			(0xF1200000)
#define EFUSE_REG_BASE			(0xF1600000)
#define AES_REG_BASE			(0xE8200000)
#define RTC_REG_BASE			(0xF1500000)
#define DDRC_REG_BASE			(0xED000000)
#define CONSOLE_REG_BASE		UART0_REG_BASE


#define FH_PMU_REG_SIZE	0x2100

#define REG_PMU_CHIP_ID                  (0x0000)
#define REG_PMU_IP_VER                   (0x0004)
#define REG_PMU_FW_VER                   (0x0008)
#define REG_PMU_SYS_CTRL                 (0x000c)
#define REG_PMU_PLL0                     (0x0010)
#define REG_PMU_PLL1                     (0x0014)
#define REG_PMU_PLL_CTRL                 (0x0018)
#define REG_PMU_CLK_GATE                 (0x001c)
#define REG_PMU_CLK_SEL                  (0x0020)
#define REG_PMU_CLK_DIV0                 (0x0024)
#define REG_PMU_CLK_DIV1                 (0x0028)
#define REG_PMU_CLK_DIV2                 (0x002c)
#define REG_PMU_CLK_DIV3                 (0x0030)
#define REG_PMU_CLK_DIV4                 (0x0034)
#define REG_PMU_CLK_DIV5                 (0x0038)
#define REG_PMU_CLK_DIV6                 (0x003c)
#define REG_PMU_SWRST_MAIN_CTRL          (0x0040)
#define REG_PMU_SWRST_AXI_CTRL           (0x0044)
#define REG_PMU_SWRST_AHB_CTRL           (0x0048)
#define REG_PMU_SWRST_APB_CTRL           (0x004c)
#define REG_PMU_SPC_IO_STATUS            (0x0054)
#define REG_PMU_SPC_FUN                  (0x0058)
#define REG_PMU_DBG_SPOT0                (0x005c)
#define REG_PMU_DBG_SPOT1                (0x0060)
#define REG_PMU_DBG_SPOT2                (0x0064)
#define REG_PMU_DBG_SPOT3                (0x0068)
#define REG_PMU_CLK_DIV7                 (0x006c)
#define REG_PMU_CLK_DIV8                 (0x0070)
#define REG_PAD_PWR_SEL                  (0x0074)
#define REG_PMU_PLL2                     (0x0078)
#define REG_PMU_PLL2_CTRL                (0x007c)

#define REG_PMU_PAD_CIS_HSYNC_CFG        (0x0080)
#define REG_PMU_PAD_CIS_VSYNC_CFG        (0x0084)
#define REG_PMU_PAD_CIS_PCLK_CFG         (0x0088)
#define REG_PMU_PAD_CIS_D_0_CFG          (0x008c)
#define REG_PMU_PAD_CIS_D_1_CFG          (0x0090)
#define REG_PMU_PAD_CIS_D_2_CFG          (0x0094)
#define REG_PMU_PAD_CIS_D_3_CFG          (0x0098)
#define REG_PMU_PAD_CIS_D_4_CFG          (0x009c)
#define REG_PMU_PAD_CIS_D_5_CFG          (0x00a0)
#define REG_PMU_PAD_CIS_D_6_CFG          (0x00a4)
#define REG_PMU_PAD_CIS_D_7_CFG          (0x00a8)
#define REG_PMU_PAD_CIS_D_8_CFG          (0x00ac)
#define REG_PMU_PAD_CIS_D_9_CFG          (0x00b0)
#define REG_PMU_PAD_CIS_D_10_CFG         (0x00b4)
#define REG_PMU_PAD_CIS_D_11_CFG         (0x00b8)
#define REG_PMU_PAD_MAC_RMII_CLK_CFG     (0x00bc)
#define REG_PMU_PAD_MAC_REF_CLK_CFG      (0x00c0)
#define REG_PMU_PAD_MAC_MDC_CFG          (0x00c4)
#define REG_PMU_PAD_MAC_MDIO_CFG         (0x00c8)
#define REG_PMU_PAD_MAC_COL_MII_CFG      (0x00cc)
#define REG_PMU_PAD_MAC_CRS_MII_CFG      (0x00d0)
#define REG_PMU_PAD_MAC_RXCK_CFG         (0x00d4)
#define REG_PMU_PAD_MAC_RXD0_CFG         (0x00d8)
#define REG_PMU_PAD_MAC_RXD1_CFG         (0x00dc)
#define REG_PMU_PAD_MAC_RXD2_MII_CFG     (0x00e0)
#define REG_PMU_PAD_MAC_RXD3_MII_CFG     (0x00e4)
#define REG_PMU_PAD_MAC_RXDV_CFG         (0x00e8)
#define REG_PMU_PAD_MAC_TXCK_CFG         (0x00ec)
#define REG_PMU_PAD_MAC_TXD0_CFG         (0x00f0)
#define REG_PMU_PAD_MAC_TXD1_CFG         (0x00f4)
#define REG_PMU_PAD_MAC_TXD2_MII_CFG     (0x00f8)
#define REG_PMU_PAD_MAC_TXD3_MII_CFG     (0x00fc)
#define REG_PMU_PAD_MAC_TXEN_CFG         (0x0100)
#define REG_PMU_PAD_MAC_RXER_MII_CFG     (0x0104)
#define REG_PMU_PAD_MAC_TXER_MII_CFG     (0x0108)
#define REG_PMU_PAD_GPIO_0_CFG           (0x010c)
#define REG_PMU_PAD_GPIO_1_CFG           (0x0110)
#define REG_PMU_PAD_GPIO_2_CFG           (0x0114)
#define REG_PMU_PAD_GPIO_3_CFG           (0x0118)
#define REG_PMU_PAD_GPIO_4_CFG           (0x011c)
#define REG_PMU_PAD_GPIO_5_CFG           (0x0120)
#define REG_PMU_PAD_GPIO_6_CFG           (0x0124)
#define REG_PMU_PAD_GPIO_7_CFG           (0x0128)
#define REG_PMU_PAD_GPIO_8_CFG           (0x012c)
#define REG_PMU_PAD_GPIO_9_CFG           (0x0130)
#define REG_PMU_PAD_GPIO_10_CFG          (0x0134)
#define REG_PMU_PAD_GPIO_11_CFG          (0x0138)
#define REG_PMU_PAD_GPIO_12_CFG          (0x013c)
#define REG_PMU_PAD_GPIO_13_CFG          (0x0140)
#define REG_PMU_PAD_GPIO_14_CFG          (0x0144)
#define REG_PMU_PAD_UART_RX_CFG          (0x0148)
#define REG_PMU_PAD_UART_TX_CFG          (0x014c)
#define REG_PMU_PAD_CIS_SCL_CFG          (0x0150)
#define REG_PMU_PAD_CIS_SDA_CFG          (0x0154)
#define REG_PMU_PAD_I2C_SCL_CFG          (0x0158)
#define REG_PMU_PAD_I2C_SDA_CFG          (0x015c)
#define REG_PMU_PAD_SSI0_CLK_CFG         (0x0160)
#define REG_PMU_PAD_SSI0_TXD_CFG         (0x0164)
#define REG_PMU_PAD_SSI0_CSN_0_CFG       (0x0168)
#define REG_PMU_PAD_SSI0_CSN_1_CFG       (0x016c)
#define REG_PMU_PAD_SSI0_RXD_CFG         (0x0170)
#define REG_PMU_PAD_SD0_CD_CFG           (0x0174)
#define REG_PMU_PAD_SD0_WP_CFG           (0x0178)
#define REG_PMU_PAD_SD0_CLK_CFG          (0x017c)
#define REG_PMU_PAD_SD0_CMD_RSP_CFG      (0x0180)
#define REG_PMU_PAD_SD0_DATA_0_CFG       (0x0184)
#define REG_PMU_PAD_SD0_DATA_1_CFG       (0x0188)
#define REG_PMU_PAD_SD0_DATA_2_CFG       (0x018c)
#define REG_PMU_PAD_SD0_DATA_3_CFG       (0x0190)
#define REG_PMU_PAD_SD1_CD_CFG           (0x0194)
#define REG_PMU_PAD_SD1_WP_CFG           (0x0198)
#define REG_PMU_PAD_SD1_CLK_CFG          (0x019c)
#define REG_PMU_PAD_SD1_CMD_RSP_CFG      (0x01a0)
#define REG_PMU_PAD_SD1_DATA_0_CFG       (0x01a4)
#define REG_PMU_PAD_SD1_DATA_1_CFG       (0x01a8)
#define REG_PMU_PAD_SD1_DATA_2_CFG       (0x01ac)
#define REG_PMU_PAD_SD1_DATA_3_CFG       (0x01b0)
#define REG_PMU_AXI0_PRIO_CFG0           (0x01b4)
#define REG_PMU_AXI0_PRIO_CFG1           (0x01b8)
#define REG_PMU_AXI1_PRIO_CFG0           (0x01bc)
#define REG_PMU_AXI1_PRIO_CFG1           (0x01c0)
#define REG_PMU_SWRSTN_NSR               (0x01c4)
#define REG_PMU_ARM_INT_0                (0x01e0)
#define REG_PMU_ARM_INT_1                (0x01e4)
#define REG_PMU_ARM_INT_2                (0x01e8)
#define REG_PMU_A625_INT_0               (0x01ec)
#define REG_PMU_A625_INT_1               (0x01f0)
#define REG_PMU_A625_INT_2               (0x01f4)
#define REG_PMU_DMA                      (0x01f8)
#define REG_PMU_WDT_CTRL                 (0x01fc)
#define REG_PMU_DBG_STAT0                (0x0200)
#define REG_PMU_DBG_STAT1                (0x0204)
#define REG_PMU_DBG_STAT2                (0x0208)
#define REG_PMU_DBG_STAT3                (0x020c)
#define REG_PMU_USB_SYS                  (0x0210)
#define REG_PMU_USB_CFG                  (0x0214)
#define REG_PMU_USB_TUNE                 (0x0218)
#define REG_PMU_PAD_CIS_CLK_CFG          (0x021c)
#define REG_PMU_USB_SYS1                 (0x0228)
#define REG_PMU_PTSLO                    (0x022c)
#define REG_PMU_PTSHI                    (0x0230)
#define REG_PMU_USER0                    (0x0234)
#define REG_PMU_PRDCID_CTRL0			 (0x500)
#define REG_PMU_PAEARCBOOT0              (0x1000)
#define REG_PMU_PAEARCBOOT1              (0x1004)
#define REG_PMU_PAEARCBOOT2              (0x1008)
#define REG_PMU_PAEARCBOOT3              (0x100c)
#define REG_PMU_PAE_ARC_START_CTRL       (0x1010)
#define REG_PMU_A625BOOT0                (0x2000)
#define REG_PMU_A625BOOT1                (0x2004)
#define REG_PMU_A625BOOT2                (0x2008)
#define REG_PMU_A625BOOT3                (0x200c)
#define REG_PMU_A625_START_CTRL          (0x2010)
#define REG_PMU_ARC_INTC_MASK            (0x2014)
#define REG_PMU_PAE_ARC_INTC_MASK        (0x2018)

/*ATTENTION: written by ARC */
#define PMU_ARM_INT_MASK             (0x01ec)
#define PMU_ARM_INT_RAWSTAT          (0x01f0)
#define PMU_ARM_INT_STAT             (0x01f4)

#define PMU_A625_INT_MASK             (0x01e0)
#define PMU_A625_INT_RAWSTAT          (0x01e4)
#define PMU_A625_INT_STAT             (0x01e8)

#define FH_GMAC_SPEED_100M	(1<<24)
#define FH_GMAC_AHB_RESET	(1<<EMAC_HRSTN_BIT)
#define PMU_RMII_SPEED_MODE (REG_PMU_SYS_CTRL)
#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG)
#define PMU_RXDV_GPIO_MASK (0x07000000)
#define PMU_RXDV_GPIO_VAL (0x01000000)

#define PMU_DWI2S_CLK_SEL_REG   (REG_PAD_PWR_SEL)
#define PMU_DWI2S_CLK_SEL_SHIFT (6)
#define PMU_DWI2S_CLK_DIV_REG   (REG_PMU_CLK_DIV6)
#define PMU_DWI2S_CLK_DIV_SHIFT (0)

#define PMU_PIX_MODE_SEL        (16)

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE		0x4000000
#define PMU_IRQ			0
#define DDRC_IRQ		1
#define WDT_IRQ			2
#define TMR0_IRQ		3
#define PAE_ARC_IRQ0		4
#define PAE_ARC_IRQ1		5
#define PAE_ARC_IRQ2		6
#define VPU_IRQ			7
#define PAE_IRQ			8
#define ISPP_IRQ		9
#define ISPF_IRQ		10
#define I2C0_IRQ		11
#define I2C1_IRQ		12
#define JPEG_IRQ		13
#define BGM_IRQ			14
#define GMAC_IRQ		15
#define AES_IRQ			16
#define SDC0_IRQ		17
#define SDC1_IRQ		18
#define ACW_IRQ			19
#define SADC_IRQ		20
#define SPI1_IRQ		21
#define SPI2_IRQ		22
#define DMAC0_IRQ		23
#define DMAC1_IRQ		24
#define I2S0_IRQ		25
#define GPIO0_IRQ		26
#define USBC_IRQ		27
#define SPI0_IRQ		28
#define ARC_SW_IRQ		29
#define UART0_IRQ		30
#define UART1_IRQ		31
#define ARM_SW_IRQ		32
#define RTC_IRQ			33
#define AHBC0_IRQ		34
#define AHBC1_IRQ		35
#define PWM_IRQ			36
#define MIPIC_IRQ		37
#define MIPI_WRAP_IRQ		38
#define WAVE420_IRQ		39
#define GPIO1_IRQ		40
#define USBC_IDHV_IRQ       41
#define USBC_OTG_IRQ        42
#define USBC_DP_IRQ		43
#define USBC_DM_IRQ		44

#define FH_UART_NUMBER 3


/* SWRST_MAIN_CTRL */
#define CPU_RSTN_BIT			(0)
#define UTMI_RSTN_BIT			(1)
#define DDRPHY_RSTN_BIT			(2)
#define DDRC_RSTN_BIT			(3)
#define PIXEL_RSTN_BIT			(6)
#define PWM_RSTN_BIT			(7)
#define SPI0_RSTN_BIT			(8)
#define SPI1_RSTN_BIT			(9)
#define I2C0_RSTN_BIT			(10)
#define I2C1_RSTN_BIT			(11)
#define ACODEC_RSTN_BIT			(12)
#define I2S_RSTN_BIT			(13)
#define UART0_RSTN_BIT			(14)
#define UART1_RSTN_BIT			(15)
#define SADC_RSTN_BIT			(16)
#define PTS_RSTN_BIT			(17)
#define TMR_RSTN_BIT			(18)
#define SPI2_RSTN_BIT			(20)
#define PAE_ARC_RSTN_BIT		(21)
#define ARC_RSTN_BIT			(22)
#define EFUSE_RSTN_BIT			(23)
#define WAVE420_ARSTN_BIT		(24)
#define WAVE420_BRSTN_BIT		(25)
#define WAVE420_CRSTN_BIT		(26)
#define SYS_RSTN_BIT			(31)

/* SWRST_AXI_CTRL */
#define JPEG_ARSTN_BIT          (2)
#define VCU_ARSTN_BIT           (3)
#define VPU_ARSTN_BIT           (4)
#define ISP_ARSTN_BIT           (5)
#define DDR_A0RSTN_BIT			(8)
#define DDR_A1RSTN_BIT			(9)
#define DDR_A2RSTN_BIT			(10)
#define X2H0_ARSTN_BIT			(11)
#define X2H1_ARSTN_BIT			(12)
#define BGM_ARSTN_BIT			(13)
#define AXI0_ARSTN_BIT			(14)
#define AXI1_ARSTN_BIT			(15)

/* SWRST_AHB_CTRL */
#define EMC_HRSTN_BIT			(0)
#define SDC1_HRSTN_BIT			(1)
#define SDC0_HRSTN_BIT			(2)
#define AES_HRSTN_BIT			(3)
#define DMAC0_HRSTN_BIT			(4)
#define INTC_HRSTN_BIT			(5)
#define JPEG_HRSTN_BIT			(8)
#define VCU_HRSTN_BIT			(9)
#define VPU_HRSTN_BIT			(10)
#define ISP_HRSTN_BIT			(11)
#define USB_HRSTN_BIT			(12)
#define HRST1N_BIT				(13)
#define HRST0N_BIT				(14)
#define ARC_HRSTN_BIT			(15)
#define PAE_ARC_HRSTN_BIT		(16)
#define EMAC_HRSTN_BIT			(17)
#define DDRC_P3_UHRSTN_BIT		(19)
#define DMAC1_HRSTN_BIT			(20)
#define H2P_HRSTN_BIT			(21)
#define BGM_HRSTN_BIT			(22)
#define HRST2N_BIT				(23)
#define HRST3N_BIT				(24)

/* SWRST_APB_CTRL */
#define ACODEC_PRSTN_BIT		(0)
#define I2S_PRSTN_BIT			(1)
#define UART1_PRSTN_BIT			(2)
#define UART0_PRSTN_BIT			(3)
#define SPI0_PRSTN_BIT			(4)
#define SPI1_PRSTN_BIT			(5)
#define GPIO_PRSTN_BIT			(6)
#define I2C0_PRSTN_BIT			(9)
#define I2C1_PRSTN_BIT			(10)
#define TMR_PRSTN_BIT			(11)
#define PWM_PRSTN_BIT			(12)
#define MIPIW_PRSTN_BIT			(13)
#define MIPIC_PRSTN_BIT			(14)
#define RTC_PRSTN_BIT			(15)
#define SADC_PRSTN_BIT      	(16)
#define EFUSE_PRSTN_BIT			(17)
#define SPI2_PRSTN_BIT      	(18)
#define WDT_PRSTN_BIT      	    (19)
#define WAVE420_PRSTN_BIT		(20)
#define DDRPHY_PRSTN_BIT    	(21)
#define DDRC_PRSTN_BIT			(22)
#define X2P0_PRSTN_BIT			(24)
#define X2P1_PRSTN_BIT      	(25)

/* FH Serial HardWare HandShake */
#define UART1_TX_HW_HANDSHAKE   (9)
#define UART1_RX_HW_HANDSHAKE   (8)
#define UART1_DMA_TX_CHAN       (2)
#define UART1_DMA_RX_CHAN       (3)

/* timer clk */
#define TIMER_CLK			(50000000)

/*sdio*/
#define SIMPLE_0     (0)
#define SIMPLE_90    (1)
#define SIMPLE_180   (2)
#define SIMPLE_270   (3)


#define SDIO0_RST_BIT       (~UL(1<<2))
#define SDIO0_CLK_RATE      (50000000)
#define SDIO0_CLK_DRV_SHIFT (20)
#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO0_CLK_SAM_SHIFT (16)
#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0)


#define SDIO1_RST_BIT       (~UL(1<<1))
#define SDIO1_CLK_RATE      (50000000)
#define SDIO1_CLK_DRV_SHIFT (12)
#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO1_CLK_SAM_SHIFT (8)
#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0)

/*usb*/
#define IRQ_UHOST          USBC_IRQ
#define FH_PA_OTG          USBC_REG_BASE
#define IRQ_OTG            IRQ_UHOST
#define FH_SZ_USBHOST	   SZ_1M
#define FH_SZ_OTG          SZ_1M

#define USB_UTMI_RST_BIT      (0x1<<1)
#define USB_PHY_RST_BIT       (0x11)
#define USB_SLEEP_MODE_BIT    (0x1<<24)
#define USB_IDDQ_PWR_BIT    (0x1<<10)
#define USB_TUNE_ADJ_SET	(0x78203344)

#endif /* __ASM_ARCH_FH8856_H */
